Apparatus having a titanium alloy layer

ABSTRACT

Structures within semiconductor devices having a titanium alloy layer are provided. The titanium alloy layer is formed through chemical vapor deposition by combining a first precursor with a reducing agent to form a seed layer, and by combining a second precursor with the seed layer to form the titanium alloy layer. Structures are described having a titanium alloy layer on sidewalls and an exposed base layer of a contact hole. Structures are further described having a titanium alloy layer on sidewalls of a contact hole and a titanium silicide layer on an exposed base layer of the contact hole. The structures are useful as device contacts to active areas of a semiconductor device, and as interlevel vias within semiconductor integrated circuits.

This application is a divisional of U.S. Ser. No. 09/030,705, filed Feb.25, 1998.

FIELD OF THE INVENTION

The present invention relates to a method for manufacturingsemiconductor devices, and more particularly, to a method for depositingconformal titanium layers on a substrate.

BACKGROUND OF THE INVENTION

Device density in integrated circuits (ICs) is constantly beingincreased. To enable the increase in density, device dimensions arebeing reduced. As the dimensions of device contacts get smaller, devicecontact resistance increases, and device performance is adverselyaffected. Methods for decreasing device contact resistance in ICs areneeded to obtain enhanced device and IC performance.

Device contacts with reduced resistance may be created by formingcertain metals on a silicon semiconductor base layer. These metals reactwith the underlying silicon, for example, to form silicides. Silicidedevice contacts are desirable because they reduce the native oxide onsilicon. The native oxide is undesirable because it increases thecontact resistance.

In one embodiment, titanium is used to form silicide device contacts fortwo reasons. First, titanium silicide has superior gettering qualities.Also, titanium silicide forms low resistance contacts on bothpolysilicon and single-crystal silicon.

Titanium siuicide device contacts are normally formed with the followingprocess. First, a thin layer of titanium is formed on top of the siliconbase layer, such as a substrate. The titanium adjoins active regionsexposed by contact holes in an isolating layer, such as an oxide, abovethe silicon base layer. Then, the silicon base layer is annealed. As aresult, the titanium reacts with the active regions of silicon to formtitanium silicide.

However, because titanium cannot be readily deposited in a pure form,additional processing steps are required to form titanium silicidedevice contacts. Titanium precursors, such as titanium tetrachloride,are commonly available and can be used to form titanium. Titaniumtetrachloride, though, can only be reduced at temperatures exceeding1000 degrees Celsius with certain reducing agents. At thesetemperatures, the silicon base layer will be damaged. Therefore, thereis a need for a method of forming titanium from titanium precursors atlower temperatures.

Furthermore, the resistance of device contacts can be adverselyincreased by conductive layers coupled between the device contacts andother components. The conductive layers may be formed by the same metallayer used to form the device contacts. As device dimensions shrink, thecontact holes become relatively deeper and narrower. Also, the walls ofthe contact holes become steeper, and closer to vertical. As a result,most metal deposition techniques form conductive layers havingrelatively small step coverage, and hence relatively high resistance.Step coverage is the ratio of the thickness of the conductive layer, inthe contact hole, for example, that are substantially perpendicular andparallel to the semiconductor base layer. Thus, the effective contactresistance is increased. Therefore, there is also a need for a method offorming conductive layers having increased step coverage to reduceeffective device contact resistance.

Conformal layers of titanium having good step coverage have beenpreviously formed at lower temperatures with chemical vapor deposition.Such techniques are disclosed in U.S. Pat. Nos. 5,173,327, 5,273,783 and5,278,100, which are hereby incorporated by reference. However,alternative, effective and efficient techniques for forming titaniumfilms are desired.

SUMMARY OF THE INVENTION

The present invention provides a method, and a corresponding resultingstructure, for forming conformal titanium films supported on a substrateof an integrated circuit (IC) by forming a seed layer supported by thesubstrate, and then reducing a titanium precursor with the seed layer.In one embodiment, the seed layer comprises zinc. The seed layer isformed by combining a first precursor and a reducing agent by chemicalvapor deposition (CVD). Then, titanium is formed by combining a secondprecursor with the seed layer by CVD.

In another embodiment, the present invention may further comprise thestep of annealing the titanium to form titanium silicide. In anotherembodiment, the step of forming the seed layer further comprises thestep of forming a seed layer that is zinc according to the followingchemical process (I):

ZnR₂+H₂→Zn+alkanes,

wherein R is an alkyl group. In one embodiment, chemical process (I) isperformed at a temperature between approximately 100 and 600 degreesCelsius.

In yet another embodiment, the first precursor may be dialkyl zinc. Inyet another embodiment, the first precursor may be trimethyl zinc.

In yet another embodiment, the step of forming titanium furthercomprises the step of combining the zinc with the second precursor thatis titanium tetrachloride according to the following chemical process(II):

TiCl₄+Zn→Ti+ZnCl₂.

In one embodiment, chemical process (II) is performed at a temperaturebetween approximately 100 and 600 degrees Celsius.

In yet another embodiment, titanium may be formed in a single stepaccording to the following chemical process (III):

TiCl₄+Zn(source)→Ti+ZnCl₂

In one embodiment, chemical process (III) is performed at a temperaturebetween approximately 100 and 700 degrees Celsius.

In yet a further embodiment, the present invention may be an ICcomprising a layer of a titanium alloy, coupled to a titanium silicidecontact. In yet another embodiment, the present invention may be amemory comprising a memory array operatively coupled to a controlcircuit and an I/O circuit. The memory array, control circuit and I/Ocircuit comprise a layer of a titanium alloy coupled to titaniumsilicide contacts. In yet another embodiment, the titanium alloy maycomprise titanium and zinc.

It is a benefit of the present invention that high step coverage metallayers can be formed. Further features and advantages of the presentinvention, as well as the structure and operations of variousembodiments of the present invention, are described in detail below withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional view of a contact hole that has been etchedthrough an insulative layer to an underlying semiconductor substrate.

FIG. 1B is a cross-sectional view of the contact hole of FIG. 1A,comprising titanium and titanium silicide film.

FIG. 2 is a cross-sectional view of the contact hole of FIG. 1A,comprising a film of second reducing agent.

FIG. 3A is a cross-sectional view of the contact hole of FIG. 1A,comprising a titanium film.

FIG. 3B is a block diagram of a memory.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration specific preferredembodiments in which the inventions may be practiced. These embodimentsare described in sufficient detail to enable persons skilled in the artto practice the invention, and it is to be understood that otherembodiments may be utilized and that logical, mechanical and electricalchanges may be made without departing from the spirit and scope of thepresent invention. The terms wafer and substrate used in the followingdescription include any semiconductor-based structure having an exposedsurface with which to form the integrated circuit structure of theinvention. Wafer and substrate are used interchangeably to refer tosemiconductor structures during processing, and may include other layersthat have been fabricated thereupon. Both wafer and substrate includedoped and undoped semiconductors, epitaxial semiconductor layerssupported by a base semiconductor or insulator, as well as othersemiconductor structures well known to one skilled in the art. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims.

In order to manufacture a device contact in an integrated circuit 19, acontact hole 10, as shown in FIG. 1A, is etched through an insulatinglayer 12, such as borophosphosilicate glass (BPSG) or silicon dioxide(SiO₂). As a result, an active region 17 of underlying semiconductorbase layer or substrate 14, is exposed. A device contact is then formedon the exposed active region 17 in the following manner.

Chemical vapor deposition (CVD) is used to form a conformal layer oftitanium or titanium alloy on the integrated circuit 19 by asubsequently described method. CVD is further described in U.S. Pat. No.5,278,100. In one embodiment, the conformal layer has a step coverage ofat least one hundred percent in the contact hole 10, even for a highaspect ratio contact hole (i.e., a contact hole that is much deeper thanit is wide). As a result, a low resistance layer of titanium or titaniumalloy 16 is formed on the insulating layer 12, as shown in FIG. 1B. Aportion of the layer 16 is formed as a low resistance device contact 18of titanium silicide over the active region 17.

In another embodiment, a cold wall-hot substrate reactor is used to formthe conformal layer of titanium or titanium alloy. In one embodiment, acold wall-hot substrate reactor is used for blanket depositions as thisdesign is efficient in regard to precursor consumption. In oneembodiment, first, a conformal film of a seed layer 22 comprising zincis deposited on the insulator 12 and substrate 14, as shown in FIG. 2.The seed layer 22 is formed with CVD by combining a first reducing agent24 with a first precursor 26, which are injected into the CVD reactorwhich is represented in block form at 29. In another embodiment, theseed layer 22 that is zinc may be formed by combining a first precursor26 that is a dialkyl zinc or trimethyl zinc compound with a reducingagent 24 that is hydrogen.

When performing this step, the integrated circuit 19 is mounted on asubstrate holder in the CVD reactor 29. The substrate 14 is heated to atemperature within a range of approximately 100 to 600 degrees Celsiusand at a pressure approximately between 1 millitorr and 1 atmosphere.Alternatively, the temperature may range from approximately 300 to 550degrees Celsius, or approximately 350 to 450 degrees Celsius. In oneembodiment, the temperature is approximately 400° C. Also,alternatively, the pressure may range from approximately 10 millitorr to100 torr. In one embodiment, the pressure is approximately 1 torr. Acarrier gas of helium, argon or nitrogen may be used at a flow rate ofbetween approximately 1 and 200 sccm. Alternatively, the flow rate mayrange between approximately 20 sccm and 1 liter. In one embodiment, thepressure is approximately 200 sccm. The first precursor 26 and thereducing agent 24 contact the heated silicon base layer and insulatinglayer 12, and form the seed layer 22 on the integrated circuit 19. Thischemical process (I) is exemplified below:

ZnR₂(gas)+H₂(gas)→Zn(solid)+alkanes(gas), where R is an alkylgroup.  (I)

First reaction products 28, such as gaseous alkanes, resulting from theformation of the seed layer 22 exit from the CVD reactor 29 through anexhaust manifold. The thickness of the seed layer 22 formed on theintegrated circuit 19 is between approximately 5 and 50 angstroms.However, the present invention envisions forming a seed layer 22 that isthicker.

Next, the seed layer 22 is converted to a layer 16 of titanium or atitanium alloy. As illustrated in FIG. 3A, a titanium precursor 32, suchas titanium tetrachloride, is combined with the seed layer 22 by CVD toform a conformal layer 16 of titanium or titanium alloy in lieu of theseed layer 22.

When performing this step, the integrated circuit 19 is mounted andheated in the CVD reactor 29 to a temperature within a range ofapproximately 100 to 600 degrees Celsius and at a pressure approximatelybetween 1 millitorr and 1 atmosphere. Alternatively, the temperature mayrange from approximately 100 to 700 degrees Celsius, approximately 300to 550 degrees Celsius, or approximately 350 to 450 degrees Celsius. Inone embodiment, the temperature is approximately 400° C. Also,alternatively, the pressure may range from approximately 10 millitorr to100 torr. In one embodiment, the pressure is approximately 1 torr. Acarrier gas of helium, argon or nitrogen may be used at a flow ofbetween approximately 1 and 200 sccm. Alternatively, the flow rate mayrange between approximately 20 sccm and 1 liter. In one embodiment, thepressure is approximately 200 sccm. When the titanium precursor 32contacts the seed layer 22 on the integrated circuit 19, the compoundsform a conformal layer 16 of titanium or a titanium alloy. The chemicalprocess (II) is exemplified below:

TiCl₄(gas)+Zn(solid)→Ti(solid)+ZnCl₂(gas)  (II)

Second reaction products 34 resulting from the formation of the titaniumor titanium alloy exit from the CVD reactor 29 through the exhaustmanifold. Part or all of the seed layer 22 is respectively converted toa layer 16 of titanium or titanium alloy. Thus, for example, when theseed layer 22 is zinc, one atom of zinc on the integrated circuit 19 isreplaced with one atom of titanium. Hence, the layer 16 of titanium, ortitanium alloy, formed on the integrated circuit 19 will have about thesame thickness as the originally deposited zinc. If this process step isconducted for a sufficient period of time, all of the seed layer 22 willbe converted to a layer 16 of titanium. However, if not all of the seedlayer 22 is converted to a layer 16 of titanium, a layer 16 of titaniumalloy, including the seed layer 22, will be formed on the integratedcircuit 19. These steps may be repeated to form thicker layers.

In another embodiment, the layer 16 of titanium or titanium alloy can beformed during a single CVD step, as exemplified by chemical process(III) below:

TiCl₄+Zn(source)→Ti+ZnCl₂  (III)

The zinc can be provided from one of many types of sources, includinggaseous and solid sources. In one embodiment of such a single CVD step,the seed and titanium layers 22, 16 can be formed substantiallysimultaneously. The titanium or titanium alloy layer 16 can be formed bycombining a first precursor 26, such as a dialkyl or trimethyl zinccompound, with a reducing agent 24, such as hydrogen, and a titaniumprecursor 32, such as titanium tetrachloride. When performing the CVDstep, the integrated circuit 19 is mounted and heated in the CVD reactor29 to a temperature within a range of approximately 100 to 600 degreesCelsius at a pressure of approximately between 1 millitorr and 1atmosphere. Alternatively, the temperature may range from approximately100 to 700 degrees Celsius, approximately 300 to 550 degrees Celsius, orapproximately 350 to 450 degrees Celsius. In one embodiment, thetemperature is approximately 400° C. Also, alternatively, the pressuremay range from approximately 10 millitorr to 100 torr. In oneembodiment, the pressure is approximately 1 torr. A carrier gas ofhelium, argon or nitrogen may be used at a flow rate of betweenapproximately 1 and 200 sccm. Alternatively, the flow rate may rangebetween approximately 20 sccm and 1 liter. In one embodiment, thepressure is approximately 200 sccm. When the first precursor 26 and thereducing agent 24 contact the heated silicon base layer and insulatinglayer 12, they form the seed layer 22 on the integrated circuit 19.Then, when the titanium precursor 32 contacts the seed layer 22, aconformal layer 16 of titanium or titanium alloy is formed on theintegrated circuit. The resulting layer 16 of titanium or titanium alloyhas a thickness between approximately 5 and 50 angstroms. However, thepresent invention envisions forming a thicker layer 16 titanium ortitanium alloy. The chemical process (IV) is exemplified below:

 ZnR₂(gas)+H₂(gas)+TiCl₄(gas)→Ti(solid)+ZnCl₂(gas)+alkanes(gas), where Ris an alkyl group.  (IV)

The reaction products 28, 34 exit from the CVD reactor 29 through theexhaust manifold.

Subsequently, the integrated circuit 19 is annealed at a temperature ofbetween approximately 250 to 750 degrees Celsius. Alternatively, thetemperature may range from approximately 250 to 800 degrees Celsius. Inone embodiment, the temperature is approximately 700 degrees Celsius. Asa result, the layer 16 of titanium or titanium alloy proximate to thesilicon is converted to titanium silicide (TiSi, TiSi₂, Ti₃Si₅ orcombinations thereof) to form the low resistance device contact 18. Forvia level applications, the anneal is not required. The via comprises atungsten or aluminum fill on top of the layer 16 which is formed on topof a conductor (also represented by reference number 17) with anoptional TiN layer therebetween.

In yet another embodiment, the low resistance device contact 18 oftitanium silicide may be formed over the active region 17 when the layer16 of titanium or titanium alloy is formed by CVD on the integratedcircuit 19 at a temperature of between approximately 250 to 750 degreesCelsius. Alternatively, the temperature may range from approximately 250to 800 degrees Celsius. In one embodiment, the temperature isapproximately 700 degrees Celsius. Upon device contact 18 formation,additional metal layers, such as titanium nitride and tungsten, may besubsequently formed over the device contact 18 and layer 16 of titaniumor titanium alloy.

In another embodiment, the integrated circuit 19 is a memory 300 in FIG.3B, such as a dynamic random access memory. The memory 300 may includean array of memory cells 302, control circuit 304, I/O circuit, wordline decoder 308, digit, or bit, line decoder 310, and sense amplifier312 coupled in a manner known to one skilled in the art. Each of theaforementioned elements of the memory 300 includes contacts 18 andlayers 16 of titanium, or titanium alloy, formed in the manner describedabove.

The present invention provides high step coverage, low resistivitytitanium silicide device contacts to silicon, or titanium contacts tometal at the via level, formed at a relatively low temperature. It is tobe understood that the above description is intended to be illustrative,and not restrictive. Many other embodiments will be apparent to those ofskill in the art upon reviewing the above description. For example,other titanium precursors, such as tetradimethyl amino titanium (TDMAT)can be used to form layers 16 and device contacts 18. Additionally, thepresent invention may be implemented with any CVD apparatus 29,including hot wall reactors, cold wall reactors, radiation beam assistedreactors, plasma-assisted reactors, and the like. Furthermore, the seedlayer 22 may be formed in any manner which provides a desired thicknessfilm. Hence, the scope of the invention should, therefore, be determinedwith reference to the appended claims, along with the full scope ofequivalents to which such claims are entitled.

What is claimed is:
 1. An integrated circuit comprising: a layer of atitanium alloy; and a titanium silicide contact coupled to the layer,wherein the titanium alloy comprises titanium and zinc.
 2. A memory,comprising: a memory array comprising a layer of a titanium alloycomprising titanium and zinc, and a titanium silicide contact coupled tothe layer; a control circuit, operatively coupled to the memory array,the control circuit comprising a layer of a titanium alloy comprisingtitanium and zinc, and a titanium silicide contact coupled to the layer;an I/O circuit, operatively coupled to the memory array, the I/O circuitcomprising a layer of a titanium alloy comprising titanium and zinc, anda titanium silicide contact coupled to the layer.
 3. A contact,comprising: a titanium alloy layer formed overlying walls of a contacthole, wherein the titanium alloy layer comprises titanium and zinc; anda titanium silicide layer formed overlying an exposed silicon base layerof the contact hole.
 4. A via, comprising: a titanium alloy layer formedoverlying walls and an exposed base layer of a contact hole; and a fillcoupled to the titanium alloy layer, wherein the fill comprises a metalselected from the group consisting of tungsten and aluminum, wherein thetitanium alloy layer comprises titanium and zinc.
 5. A via, comprising:a titanium zinc alloy layer formed overlying walls and an exposed baselayer of a contact hole; a fill coupled to the titanium alloy layer,wherein the fill comprises a metal selected from the group consisting oftungsten and aluminum; and a titanium nitride layer interposed betweenthe titanium alloy layer and the fill.
 6. A via, comprising: a titaniumzinc alloy layer formed overlying walls and an exposed base layer of acontact hole; a fill comprising a metal selected from the groupconsisting of tungsten and aluminum; and; a titanium nitride layerinterposed between the titanium zinc alloy layer and the fill.
 7. Amemory device, comprising: a memory array; a control circuit operativelycoupled to the memory array; and an I/O circuit operatively coupled tothe memory array; wherein the memory device comprises at least onecontact having a titanium zinc alloy layer formed overlying walls of acontact hole and a titanium silicide layer formed overlying an exposedsilicon base layer of the contact hole.
 8. A memory device, comprising:a memory array; a control circuit operatively coupled to the memoryarray; and an I/O circuit operatively coupled to the memory array;wherein the memory device comprises a via having a titanium alloy layerformed overlying walls and an exposed base layer of a contact hole, anda fill coupled to the titanium alloy layer, and the fill comprises ametal selected from the group consisting of tungsten and aluminum,wherein the titanium alloy layer comprises titanium and zinc.
 9. Amemory device, comprising: a memory array; a control circuit operativelycoupled to the memory array; and an I/O circuit operatively coupled tothe memory array; wherein the memory device comprises at least one viahaving a titanium zinc alloy layer formed overlying walls and an exposedbase layer of a contact hole, a fill comprising a metal selected fromthe group consisting of tungsten and aluminum, and a titanium nitridelayer interposed between the titanium zinc alloy layer and the fill. 10.A memory device, comprising: a memory array; a control circuitoperatively coupled to the memory array; and an I/O circuit operativelycoupled to the memory array; wherein the memory device comprises atleast one via having a titanium zinc alloy layer formed overlying wallsand an exposed base layer of a contact hole, a fill comprising a metalselected from the group consisting of tungsten and aluminum, and atitanium nitride layer interposed between the titanium alloy layer andthe fill.
 11. The memory device of claim 7 wherein the memory arraycomprises a contact having a titanium zinc alloy layer formed overlyingwalls of a contact hole and a titanium silicide layer formed overlyingan exposed silicon base layer of the contact hole.
 12. The memory deviceof claim 7 wherein the control circuit comprises a contact having atitanium zinc alloy layer formed overlying walls of a contact hole and atitanium silicide layer formed overlying an exposed silicon base layerof the contact hole.
 13. The memory device of claim 7 wherein the I/Ocircuit comprises a contact having a titanium zinc alloy layer formedoverlying walls of a contact hole and a titanium silicide layer formedoverlying an exposed silicon base layer of the contact hole.
 14. Thememory device of claim 8 wherein the memory array comprises a via havinga titanium alloy layer formed overlying walls and an exposed base layerof a contact hole, and a fill coupled to the titanium alloy layer,wherein the titanium alloy layer comprises titanium and zinc, and thefill comprises a metal selected from the group consisting of tungstenand aluminum.
 15. The memory device of claim 8 wherein the controlcircuit comprises a via having a titanium alloy layer formed overlyingwalls and an exposed base layer of a contact hole, and a fill coupled tothe titanium alloy layer, wherein the titanium alloy layer comprisestitanium and zinc, and the fill comprises a metal selected from thegroup consisting of tungsten and aluminum.
 16. The memory device ofclaim 8 wherein the I/O circuit comprises a via having a titanium alloylayer formed overlying walls and an exposed base layer of a contacthole, and a fill coupled to the titanium alloy layer, wherein thetitanium alloy layer comprises titanium and zinc, and the fill comprisesa metal selected from the group consisting of tungsten and aluminum. 17.The memory device of claim 9 wherein the memory array comprises a viahaving a titanium alloy layer formed overlying walls and an exposed baselayer of a contact hole, a fill comprising a metal selected from thegroup consisting of tungsten and aluminum, and a titanium nitride layerinterposed between the titanium alloy layer and the fill.
 18. The memorydevice of claim 9 wherein the control circuit comprises a via having atitanium alloy layer formed overlying walls and an exposed base layer ofa contact hole, a fill comprising a metal selected from the groupconsisting of tungsten and aluminum, and a titanium nitride layerinterposed between the titanium alloy layer and the fill.
 19. The memorydevice of claim 9 wherein the I/O circuit comprises a via having atitanium alloy layer formed overlying walls and an exposed base layer ofa contact hole, a fill comprising a metal selected from the groupconsisting of tungsten and aluminum, and a titanium nitride layerinterposed between the titanium alloy layer and the fill.
 20. The memorydevice of claim 10 wherein the memory array comprises a via having atitanium zinc alloy layer formed overlying walls and an exposed baselayer of a contact hole, a fill comprising a metal selected from thegroup consisting of tungsten and aluminum, and a titanium nitride layerinterposed between the titanium alloy layer and the fill.
 21. The memorydevice of claim 10 wherein the control circuit comprises a via having atitanium zinc alloy layer formed overlying walls and an exposed baselayer of a contact hole, a fill comprising a metal selected from thegroup consisting of tungsten and aluminum, and a titanium nitride layerinterposed between the titanium alloy layer and the fill.
 22. The memorydevice of claim 10 wherein the I/O circuit comprises a via having atitanium zinc alloy layer formed overlying walls and an exposed baselayer of a contact hole, a fill comprising a metal selected from thegroup consisting of tungsten and aluminum, and a titanium nitride layerinterposed between the titanium alloy layer and the fill.